design and technology booster co-optimization.standard cell, SRAM, and digital designs.layout style and lithography co-optimization (including optical source and design co- optimization).design for multi-patterning (MP) technology.
propagating electrical design intent for RET/OPC and manufacturing optimization and verification.leveraging design-intent information (beyond layout) for manufacturing.Topics of interest include, but are not limited to:ĭesign Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) Like last year, papers should emphasize fundamentals of technical solutions rather than their commercial embodiments. This year’s conference will also include broad computational patterning topics in areas of both Optical and EUV lithography. Cost-of-ownership (CoO), yield, and reliability-related topics have been covered as well. In past years, this conference has covered the topics of design interactions with computational patterning (e.g., OPC), lithography/etch processes, fill, CMP, and other integration process. Design for Manufacturability (DFM), Design for Yield (DFY), and computational patterning are used to improve the manufacturability, while reducing the error and cost during the design phase. Design Technology Co-Optimization (DTCO) is the process to co-optimize the design and technology (i.e., manufacturing process and electronic design automation) to improve chip power, performance, area, and cost (PPAC) as the manufacturing process constraints continue to be an important consideration in semiconductor technology node definition, ramp, and scale manufacturing.